1. Field of the Disclosure
The disclosure relates to a method for manufacturing a semiconductor device and a capacitor and, more particularly, to a method for manufacturing a diffusion barrier layer used in a capacitor.
2. Description of Related Art
In a dynamic random access memory (DRAM) and a ferroelectric RAM (FeRAM), a capacitor generally includes a bottom electrode, a high dielectric layer, and a top electrode.
Among various semiconductor memory devices, the DRAM is a memory device with excellent integration because one unit cell is composed of one transistor and one capacitor.
With progress of integration technology, the memory capacity of semiconductor device is increased about four times every three years. For example, 256 Mb DRAM and GB level of DRAM have been developed.
As integration of DRAM proceeds, a memory cell dimension is decreased gradually. For example, in the case of 256 Mb DRAM, the memory cell dimension is 0.5 μm2, and, in this case, a capacitor dimension, which is one of basic element of a cell, may be smaller than 0.3 μm2.
To obtain high capacitance in a small memory cell, numerous methods may be used. For example, the dielectric layer of the capacitor may be formed with a material having high dielectric constant, or the thickness of the dielectric layer is reduced, or the surface area of the capacitor is increased.
To increase the surface area of the capacitor, that is to increase the surface area of the charge storage electrode, there are provided numerous capacitor manufacturing technologies, such as stack-type capacitor or a trench-type capacitor formation technology, or a hemispherical polysilicon grain formation technology for forming the charge storage electrode. However, the above-mentioned technologies complicated capacitor structure, and the manufacturing process is very intricate, thereby increasing the cost of a product and decreasing the yield of the process.
Generally, SiO2/Si3N4-based dielectric materials are used as the capacitor dielectric layer, and there exists a technological limit in the method for increasing capacitance by decreasing a thickness of a SiO2/Si3N4-based dielectric layer.
Therefore, a method for capacitor manufacturing using high dielectric materials, such as Ta2O5, SrBi2Ta2O9 (hereinafter, referred to as a SBT) having a perovskite structure, Pb(Zr, Ti)O3 (hereinafter, referred to as a PZT) and (Bi, La)4Ti3O12 (hereinafter, referred to as a BLT), which have higher dielectric constant than the SiO2/Si3N4 based dielectric materials, are proposed.
Such high dielectric materials are used to increase memory device integration. With the use of high dielectric materials, the problem of bottom electrode oxidation is encountered. Therefore, research for forming the bottom electrode with a metal or a conductive oxide material, such as Pt, Ru, RuO2, Ir and IrO2, has been undertaken.
Meanwhile, to apply the above-mentioned metal or the conductive oxide material for forming the bottom electrode, a diffusion barrier layer is necessarily formed between the bottom electrode and a polysilicon plug for connecting the bottom electrode to a semiconductor substrate. A diffusion barrier layer may have good characteristics in preventing diffusion of oxygen generated in a dielectric formation process, which is processed in an O2 atmosphere at a temperature of over 600° C.
Diffusion barrier layers formed in accordance with conventional methods are reactive with oxygen, nonconductive products are formed due to the oxidation of the diffusion barrier layer, and an erroneous operation of a capacitor is occurred.